Programmable voltage divider and method for testing the impedance of a programmable element

ABSTRACT

A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled node, a second divider element that has a selectable resistivity and that is coupled between the divider node and the controlled node, and a test circuit that is coupled between the controlled node and the second supply node. During the normal mode of operation, the first and second divider elements generate the data value having a first logic level when the second divider element has a first resistivity, and generate the data value having a second logic level when the second divider element has a second resistivity. The test circuit generates a first voltage at the controlled node during the normal mode of operation, and generates a second voltage at the controlled node during the test mode of operation. The test circuit may generate the first and second voltages by varying its impedance, or by switching in and out one or more fixed voltages.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The following pending U.S. Patent Applications entitled: “AnEfficient Method of Determining Acceptable Resistance of a Blown Fuse,”Attorney Docket No. MCRO:181, filed Mar. 7, 1997, and “Method andApparatus for Checking the Resistance of Antifuses,” Attorney Docket No.MCRO:251, filed Mar. 7, 1997, are related to the present application.

TECHNICAL FIELD

[0002] The present invention relates generally to electronic circuits,and more specifically to a programmable circuit that allows one to testthe impedance of a programmable element, such as a fuse, during a testmode, and to a method for performing such a test.

BACKGROUND OF THE INVENTION

[0003] Many of today's integrated circuits, such as memory circuits, areprogrammable to operate in one or more particular modes, or to have oneor more particular circuit configurations. An example of the latter typeof circuit is a memory that includes redundant memory columns forreplacing defective array memory columns. When a circuit testerdiscovers a defective array column, it programs the memory such thatwhen an external device addresses the defective column, data is routedto a selected redundant column in a manner that is transparent to theexternal device. Typically, the manufacturer programs such integratedcircuits at the factory before shipping them to customers.

[0004] These integrated circuits each typically include a bank ofnonvolatile, programmable memory elements that the manufacturer programsto set a circuit in the desired operational mode or circuitconfiguration. Examples of such elements include electrically erasableand programmable read-only memory (EEPROM) cells, fuses, and antifuses.An integrated circuit often incorporates into its programmable bank thetype of programmable element that is the most similar to other elementsor components of the circuit. For example, a Flash-EEPROM device oftenincludes a bank of EEPROM cells, but a dynamic random access memory(DRAM often includes a bank of antifuses, which are similar in structureto the DRAM storage capacitors. Furthermore, such a programmable elementtypically has a first impedance in an unprogrammed state, and a second,different impedance in a programmed state. For example, an antifuse hasa high impedance in an unprogrammed state, and thus is essentially anopen circuit, and has a low impedance in a programmed state, and thus isessentially a short circuit. Conversely, a fuse is essentially a shortcircuit in an unprogrammed state, and is essentially an open circuit ina programmed state.

[0005] But because a programmed element may not always have an impedancethat is within a desired range, the manufacturer often measures theimpedances of the programmed elements in an analog fashion after itfinishes programming the entire programmable bank. The analog testerperforms these measurements sequentially by placing a voltage acrosseach programmed element and measuring the current therethrough. If themanufacture discovers a programmed element that does not have thedesired impedance, it can reprogram the element one or more times untilit has the desired impedance.

[0006] A problem with this analog testing technique is that it oftentakes too long for high-density integrated circuits. As the number ofcircuit components in an integrated circuit increases, so does thenumber of operational modes and circuit configurations that the circuitsupports. Therefore, the number of programmable elements in theprogrammable bank also increases to accommodate the additionaloperational modes and circuit configurations. For example, a 4 megabitDRAM may have 20 antifuses in its programmable bank, but a 64 megabitDRAM may have 640 antifuses. Furthermore, measuring the impedance in ananalog fashion is relatively slow because of the parasitic capacitancesassociated with the test path and each programmed element. Thus,increasing the storage capacity of a DRAM by a factor of 16 canpotentially increase the number of antifuses, and thus the alreadylengthy testing time, by a factor of 32. Additionally, testers that canperform analog measurements are often expensive and complicated tooperate in the analog-testing mode.

SUMMARY OF THE INVENTION

[0007] In accordance with one aspect of the present invention, aprogrammable voltage divider has normal and test modes of operation. Thedivider includes first and second supply nodes, a divider node thatprovides a data value, and a first divider element that is coupledbetween the first supply node and the divider node. The divider alsoincludes a controlled node, a second divider element that has aselectable resistivity and that is coupled between the divider node andthe controlled node, and a test circuit that is coupled between thecontrolled node and the second supply node. The test circuit generates avoltage at the controlled node during the normal mode of operation, andvaries this voltage during the test mode of operation.

[0008] In a related aspect of the present invention, the test circuitincludes a first switch coupled between the controlled node and thesecond supply node and a series combination of a second switch and avoltage source, the series combination coupled in parallel with thefirst switch. During the test mode, the test circuit opens the firstswitch and closes the second switch.

[0009] In another related aspect of the invention, the test circuitincludes a first switch coupled between the controlled node and thesecond supply node, and a series combination of a second switch and animpedance element, the series combination coupled in parallel with thefirst switch. During the test mode, the test circuit opens the firstswitch and closes the second switch.

[0010] In yet another related aspect of the invention, the test circuitincludes a first switch coupled between the controlled node and thesecond supply node, and a diode coupled in parallel with the firstswitch. During the test mode, the test circuit opens the first switch.

[0011] An advantage of the present invention is that it allows fastertesting of programmable elements as compared with the prior art. Anotheradvantage is that the present invention allows digital testing ofprogrammable elements instead of analog testing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic diagram of a programmable bank according toa first embodiment of the invention.

[0013]FIG. 2 is a schematic diagram of a programmable bank according toa second embodiment of the invention.

[0014]FIG. 3 is a schematic diagram of a first alternative embodiment ofthe test circuit of FIG. 2.

[0015]FIG. 4 is a schematic diagram of a second alternative embodimentof the test circuit of FIG. 2.

[0016]FIG. 5 is a schematic diagram of a programmable bank according toa third embodiment of the invention.

[0017]FIG. 6 is a schematic diagram of an alternative embodiment of theprogrammable elements of FIGS. 1, 2 and 5.

[0018]FIG. 7 is a schematic diagram of a programmable bank according toa fourth embodiment of the invention.

[0019]FIG. 8 is a schematic block diagram of a memory device thatincorporates a programmable bank according to the present invention.

[0020]FIG. 9 is a schematic block diagram of a computer system thatincorporates the memory device of FIG. 8.

DETAILED DESCRIPTION OF THE INVENTION

[0021]FIG. 1 is a schematic diagram of a programmable bank 10 accordingto a first embodiment of the invention. The bank 10 includesindividually programmable circuits 12 ₀-12 _(n), which generate binaryreference signals P₀-P_(n) at respective output nodes 14 ₀-14 _(n). Theactual logic levels of the signals P₀-P_(n) depend upon the states inwhich the circuits 12 ₀-12 _(n) are programmed. The integrated circuit(not shown in FIG. 1) that incorporates the bank 10 uses the signalsP₀-P_(n) to select its operational modes or to configure its circuitry.The bank 10 also includes a test circuit 16, which allows themanufacturer to test the programmable circuits 12 ₀-12 _(n) in a digitalmanner, i.e., by merely reading the values P₀-P_(n). Thus, themanufacturer can test the bank 10 in a manner that is both faster andeasier than prior testing techniques. Furthermore, the bank 10 maysupport conventional analog testing as well as the inventive digitaltesting. The bank 10 is discussed below in greater detail with specificreference to the programmable circuit 12 ₀, which is similar instructure and operation to the other programmable circuits 12 ₁-12 _(n).

[0022] The programmable circuit 12 ₀ includes a programmable element 18₀, which is an antifuse in this first embodiment of the invention. Afirst node of the antifuse 18 ₀ is coupled to a test node 20, which iscommon to the first nodes of all the antifuses 18 ₀-18 _(n). A secondnode is coupled to an isolation device 19 ₀, which limits the voltageacross the antifuse 18 ₀ during normal operation of the bank 10. In oneaspect of the invention, the device 19 is an NMOS transistor, which hasits gate coupled to a voltage V₁ during normal operation of the bank 10,and to 0 V, i.e., ground, during programming of the bank 10.

[0023] The circuit 12 ₀ also includes a latch/pull-up circuit 22 ₀,which generates the signal P₀ in response to the state of the antifuse18 ₀. The circuit 22 ₀ includes an inverter 24 ₀, which has an inputterminal coupled to a reference node 25 ₀. The circuit 22 ₀ alsoincludes a feedback switch 26 ₀, which together with the inverter 2 ₄₀forms a latch 27 ₀, an impedance element, e.g., a pull-up or dividerdevice 28 ₀, and an initialization switch 30 ₀, which allows the circuit22 ₀ to generate the desired value for P₀ during the initial power-up ofthe integrated circuit that incorporates the bank 10. In one aspect ofthe invention, the feedback switch 26 ₀ and the initialization switch 30₀ are PMOS transistors, and the pull-up device 28 ₀ is acontrolled-current, i.e., long-channel, PMOS transistor. An advantage ofthe circuit 22 ₀ is that after the initialization pulse is removed, thecircuit 12 ₀ draws no quiescent supply current regardless of whether theantifuse 18 ₀ is programmed or unprogrammed.

[0024] In addition to the circuits 12 ₀-12 _(n), the programmable bank10 also includes programming/analog-testing circuitry 32, which iscoupled across each of the antifuses 18 ₀-18 _(n). The programmingcircuitry 32 includes a program/test circuit 34, which provides aprogramming voltage at the common node 20 to program selected ones ofthe antifuses 18 ₀-18 _(n). A tester (not shown in FIG. 1) can becoupled to the common node 20 to provide a test voltage and measure theresultant test current to determine the impedances of the antifuses 18₀-18 _(n) in an analog fashion. A program/decoder 36 couples to groundthe first node of an antifuse 18 that is selected for either programmingor analog testing.

[0025] The bank 10 further includes a bank-mode circuit 37, whichincludes the test circuit 16, a normal-mode switch 38, and aconventional mode-control circuit 44. The switch 38 couples the commonnode 20 to ground during normal operation of the bank 10. The testcircuit 16 includes a switch 40 that couples the test node to groundthrough an impedance element 42 in a test mode during digital testing ofthe bank 10. The mode-control circuit 44 controls the switch 38 and theswitch 40 of the test circuit 16. In one embodiment of the invention,the switches 38 and 40 are NMOS transistors, and the impedance element42 is a resistor. In other embodiments of the invention, the impedanceelement 42 can be a long-channel PMOS transistor or any otherconventional impedance device.

[0026] Still referring to FIG. 1, in operation during programming of theantifuse 18 ₀, the gate of the isolation transistor 19 ₀ is coupled toground such that the transistor 19 ₀ is inactive, and thus electricallyisolates the antifuse 18 ₀ from the latch/pull-up circuit 22 ₀. Thedecoder 36 couples the first node of the antifuse 18 ₀ to ground. Theprogram/test circuit 34 then provides on the common node 20 aprogramming voltage that programs or “blows” the antifuse 18 ₀, i.e.,significantly lowers the impedance between its first and second nodes.In one aspect of the invention, the programming voltage is between 7 Vand 9 V. Once programmed, the antifuse 18 ₀ should be essentially ashort circuit.

[0027] During optional and conventional analog testing of the programmedantifuse 18 ₀, the program/test circuit 34 provides a test voltage onthe common node 20, and a conventional tester (not shown in FIG. 1)measures the current through the antifuse 18 ₀. If the measuredimpedance is less than a desired maximum impedance, the antifuse 18 ₀passes the test and is deemed to have been properly programmed. In oneaspect of the invention, the desired maximum impedance is 300 ohms.

[0028] During normal operation, the program/test circuit 34 is inactive,and the decoder 36 uncouples the antifuse 18 ₀ from ground. Furthermore,the gate of the isolation transistor 19 ₀ is coupled to the voltage V₁,which in one embodiment of the invention, is approximately Vcc/2. Thus,if Vcc=5V, V₁=2.5V. In normal operation, the mode-control circuit 44also turns off the transistor 40 to deactivate the test circuit 16, andturns on the switch 38, which couples the common node 20 to ground. Aninitialization pulse then activates the switch 30 ₀ for a timesufficient to set the latch 27 ₀, which generates P₀ equal to logic 1 ifthe antifuse 18 ₀ is programmed, or generates P₀ equal to logic 0 if theantifuse 18 ₀ is unprogrammed. Specifically, during normal operationwhen the initialization pulse is present and the antifuse 18 ₀ isprogrammed to have a low impedance, a relatively large current flowsthrough the switch 30 ₀, the pull-up device 28 ₀, the active isolationtransistor 19 ₀, and the antifuse 18 ₀. The programmable circuit 12 ₀acts as a voltage divider and generates a reference voltage at thereference node 25 ₀. Because the antifuse 18 ₀ has a relatively lowimpedance, which is typically no more that a few hundred ohms, thereference voltage is low enough to represent a logic 0, and thus theinverter 24 ₀ generates P₀ equal to logic 1. The logic 1 at the output14 ₀ of the inverter 24 ₀ turns off the feedback switch 26 ₀. After theinitialization pulse is removed, the inactive feedback switch 26 ₀reinforces the logic 0 at the input of the latch 24 ₀ so that the signalP₀ remains equal to logic 1.

[0029] During normal operation when the initialization pulse is presentand the antifuse 18 ₀ is unprogrammed to have a high impedance, littleor no current flows through the switch 30 ₀, the pull-up device 28 ₀,the isolation transistor 19 ₀, and the antifuse 18 ₀. Thus, the device28 ₀ pulls up the reference voltage at the node 25 ₀ to approximatelyVcc, which is high enough to represent a logic 1, and the inverter 24 ₀generates P₀ equal to logic 0, which turns on the feedback switch 26 ₀.After the initialization pulse is removed, the active feedback switch 26₀ reinforces the logic 1 at the input of the latch 24 ₀ so that thesignal P₀ remains equal to logic 0. Furthermore, the isolationtransistor 19 ₀ maintains the voltage at the first node of the antifuse18 ₀ at one threshold voltage below V₁, which as stated above isapproximately Vcc/2 in one aspect of the invention. Thus, the transistor19 ₀ insures that during normal operation, the voltage across theunprogrammed antifuse 18 ₀ is too low to accidentally program it.

[0030] In operation during a digital test mode according to the firstembodiment of the present invention, the programmed antifuses 18 ₀-18_(n) are tested to make sure that they are properly programmed, i.e.,that their resistance is less than a desired maximum value. After theantifuse 18 ₀ has been programmed, the programmed resistance of theantifuse 18 ₀ is tested. During testing, the circuit 12 ₀ operates in amanner similar to the normal operating mode described above, except thatthe mode-control circuit 44 shuts off the switch 38, and turns on theswitch 40, thereby coupling the common node 20 to ground through theimpedance element 42. The impedance element 42 effectively increases theimpedance of the antifuse 18 ₀, i.e., increases the impedance of thelower leg of the voltage divider, and thus increases the referencevoltage at the node 25 ₀. Therefore, if the circuit 12 ₀ generates P₀equal to logic 1 when the impedance element 42 is coupled between theantifuse 18 ₀ and ground, then the manufacturer can be virtually certainthat the circuit 12 ₀ will generate P₀ equal to logic 1 during normaloperation when the active switch 38 couples the antifuse 18 ₀ directlyto ground. Conversely, if during the digital test mode the circuit 12 ₀generates P₀ equal to logic 0, then the manufacturer knows that theantifuse 18 ₀ is improperly programmed, or not programmed at all. Atthis point, one can instruct the programming circuitry 32 to reprogramthe antifuse 18 ₀. Or, if the circuit 12 ₀ is expendable, it can belabeled as defective and not used.

[0031] For example, if the maximum desired impedance for the antifuse 18₀ is 300 ohms, and 500 or more ohms between the node 25 ₀ and groundwill cause the reference voltage to be equivalent to logic 1 instead oflogic 0, then the impedance element 42 has a value of approximately 200ohms. Thus, during the digital test mode, if the impedance of theantifuse 18 ₀ is greater than the maximum desired impedance of 300 ohms,the combined impedance between the node 25 ₀ and ground is greater thanor equal to 500 ohms, and P₀ equals logic 0. Conversely, if theimpedance of the antifuse 18 ₀ is less than the maximum desiredimpedance, the combined impedance is less than 500 ohms, and P₀ equalslogic 1.

[0032] In one embodiment of the invention, all of the signals P₀-P_(n)are coupled to a multiplexer (not shown in FIG. 1), which provides aselected one of the signals to an external pin of the device in whichthe bank 10 is incorporated so that a tester can sequentially read thesignals P₀-P_(n) without internally probing the device.

[0033] Thus, the digital test mode according to the first embodiment ofthe invention allows a manufacturer to use a tester that need only readdigital values instead of measuring an impedance in an analog fashion. Atester that reads only digital values is often less expensive topurchase and operate than one that must measure analog values.Furthermore, such a tester is often easier to operate. Additionally,even a tester that supports both digital and analog testing is ofteneasier and cheaper to operate in the digital mode.

[0034] Moreover, the digital technique is often faster than prior analogtechniques. Specifically, in the digital test mode, all the antifuses 18₀-18 _(n) are connected so that the circuits 12 ₀-12 _(n) areoperational. Thus, one need only switch a multiplexer or move a probefrom one signal P to the next, with no delay other than the multiplexerswitching or probe movement time, which are often relatively shortConversely, in the prior analog testing, each antifuse 18 must beindividually switched into the test circuit. Because of the parasiticcapacitances and inductances associated with the antifuses 18 and thebank 10 in general, after switching each antifuse 18 into the testcircuit, one must wait a relatively long settling time before measuringthe current therethrough. Thus, the greater the number of programmedantifuses 18 being tested, the more time the inventive digital techniquewill save over the prior analog technique.

[0035]FIG. 2 is a schematic diagram of a programmable bank 46 accordingto a second embodiment of the invention. The bank 46 is similar instructure and operation to the bank 10 of FIG. 1, except that in placeof the impedance device 42, a test circuit 47 includes a voltage source48, such as a battery, that generates a positive test voltage VT on thecommon node 20 during the digital test mode. The test voltage VT has thesame affect as discussed above for the impedance 42 of FIG. 1 in that itboosts the reference voltage at the node 25 ₀, and thus effectivelyincreases the impedance of the antifuse 18 ₀ during digital testing. Inone embodiment of the invention, VT is between 0.7 V and 1.5 V.

[0036]FIG. 3 is a schematic diagram of a test circuit 49 according to afirst alternative embodiment of the invention. Specifically, the testcircuit 49 can be used in place of the test circuit 47 of FIG. 2. In thetest circuit 49, the voltage source 48 is a forward-biased PN junctiondiode 50, which generates a positive test voltage of approximately 0.7 Vduring the digital test mode when the switch 38 of FIG. 2 is inactive.

[0037]FIG. 4 is a schematic diagram of a test circuit 51 according to asecond alternative embodiment of the invention. The test circuit 51 issimilar to the test circuit 49 of FIG. 3, except that it includes adiode-connected NMOS transistor 52 instead of a PN junction diode. In arelated embodiment of the invention, the test circuit 51 may include adiode-connected bipolar NPN transistor (not shown in FIG. 4) instead ofthe NMOS transistor 52.

[0038]FIG. 5 is a schematic diagram of a programmable bank 54 accordingto a third embodiment of the invention. The bank 54 is similar to thebank 10 of FIG. 1 and the bank 46 of FIG. 2, except that programmablecircuits 59 ₀ include programmable elements 56 ₀-56 _(n), and a testcircuit 55 includes a voltage source 58, which generates a negativevoltage -VT on the common node 20 during the digital test mode. In oneaspect of the invention, the elements 56 ₀-56 _(n) are eitherlaser-cutable fuses or electrically programmable fuses. Thus, unlike theantifuses 18 ₀-18 _(n) of FIGS. 1 and 2, the fuses 56 ₀-56 _(n) have alow impedance when unprogrammed, and have a high impedance whenprogrammed. Because the fuses 56 ₀-56 _(n) are not antifuses, theprogramming circuitry 32 and the isolation transistors 19 of the banks10 and 46 may be omitted. In this case, the fuses 56 ₀-56 _(n) areprogrammed using conventional means (not shown in FIG. 5) that areexternal to the device that incorporates the bank 54. Alternatively, ifthe fuses 56 ₀-56 _(n) are electrical fuses, then the bank 54 mayinclude circuitry that is similar to the programming circuitry 32 ofFIGS. 1 and 2. But for clarity, FIG. 5 includes no programmingcircuitry. Because the circuit 59 ₀ is similar in structure andoperation to the circuits 59 ₁-59 _(n), the operation of the bank 54 isdiscussed below in greater detail with reference to the circuit 59 ₀ forclarity.

[0039] During optional conventional analog testing of the element 56 ₀,a technician uses an ohmmeter (both not shown in FIG. 5) to measure theimpedance of the fuse 56 _(0.)

[0040] During normal operation, the bank 54 operates as described abovein conjunction with the bank 10 of FIG. 1 and the bank 46 of FIG. 2,except that the circuit 59 ₀ generates P₀ equal to logic 0 when the fuse56 ₀ is programmed, and generates P₀ equal to logic 1 when the fuse 56 ₀is unprogrammed. Again, this is because in contrast to the antifuses 18₀-18 _(n) of FIGS. 1 and 2, the fuses 56 ₀-56 _(n) have a high impedancewhen programmed, and a low impedance when unprogrammed.

[0041] During a digital test mode, the programmed fuses 56 ₀-56 _(n) aretested to make sure that they are properly programmed, i.e., that theirprogrammed resistance is greater than a desired minimum value. When thefuse 56 ₀ is programmed, the circuit 59 ₀ operates like it does duringnormal mode, except that the mode-control circuit 44 shuts off theswitch 38, and turns on the transistor 40 to activate the test circuit55 and couple the negative test voltage −V_(T) to the common node 20.−V_(T) effectively decreases the impedance of the fuse 56 ₀ and thusdecreases the reference voltage at the node 61 ₀ as compared with normaloperation. Therefore, if the circuit 59 ₀ generates P₀ equal to logic 0when −V_(T) is on the common node 20, then the manufacturer can bevirtually certain that the circuit 59 ₀ will generate P₀ equal to logic0 during normal operation when the active switch 38 couples the commonnode 20 directly to ground. Conversely, if during the digital test modethe circuit 59 ₀ generates P₀ equal to logic 1, then the manufacturerknows that the fuse 56 ₀ is improperly programmed, or not programmed atall. At this point, the manufacturer can reprogram the fuse 56 ₀, or, ifthe circuit 59 ₀ is expendable, can label it as defective and not useit.

[0042] For example, using the conventional voltage-divider equation:$V_{r} = {\frac{R_{a}}{R_{a} + R_{b}} \times V}$

[0043] where V_(r) is the reference voltage at the node 61 ₀, if Vccequals 5 V, the threshold between logic 1 and logic 0 is approximately2.5 V, the impedance of the element 28 ₀ is 10 kilohm, and the desiredminimum impedance of the fuse 56 ₀ is 40 kilohm, then −VT=−7.5 V. Thus,during the digital test mode, if the impedance of the fuse 56 ₀ is lessthan the desired minimum impedance, P₀ will equal logic 1. Conversely,if the impedance of the fuse 56 ₀ is greater than the desired minimumimpedance, P₀ will equal logic 0.

[0044] As discussed above in conjunction with FIG. 1, all of the signalsP₀-P_(n) may be coupled to a multiplexer (not shown in FIG. 5), whichprovides a selected one of the signals to an external pin of the devicein which the bank 54 is incorporated so that a tester can sequentiallyread the signals P₀-P_(n.)

[0045]FIG. 6 is a schematic diagram of nonvolatile programmable element60 according to an alternative embodiment of the invention. Theprogrammable element 60 is a EEPROM cell that includes a floating gate62. In a conventionally defined unprogrammed state, there is no voltagestored on the floating gate 62, and thus the EEPROM cell 60 has a lowimpedance, i.e., acts as a closed circuit, when a voltage is applied toits gate. In a conventionally defined programmed state, a negativevoltage is stored on the floating gate 62, and thus the EEPROM cell 60has a high impedance, i.e., acts as an open circuit, when a voltage isapplied to its gate. Thus, the EEPROM cell 60 is similar to the fuseelements 56 ₀-56 _(n) of FIG. 5, and in one aspect of the invention maybe used in place of these fuse elements in the bank 54.

[0046] Still referring to FIG. 6, one can unconventionally define theunprogrammed state as when the floating gate 62 has a negative voltagestored thereon, and the programmed state as when there is no voltagestored on the floating gate 62. Using this unconventional definition,the EEPROM cell 60 resembles the antifuses 18 ₀-18 _(n) of FIG. 1. Thus,in an aspect of the invention using these unconventional definitions ofthe programmed and unprogrammed states, EEPROM cells like the cell 60may be used in place of the antifuse elements 18 ₀-18 _(n) in the bank10 of FIG. 1. If, however, one decides to use this unconventionaltechnique, he has to first “unprogram” all of the cells 60 by storingnegative voltages on the floating gates 62 thereof.

[0047]FIG. 7 is a schematic block diagram of a programmable bank 64according to a fourth embodiment of the invention. The bank 64 allowssimultaneous digital testing of more than one programmable circuit 66₀-66 ₃ at a time. Although the four circuits 66 ₀-66 ₃ are shown herefor clarity, the bank 64 may include more or less of these circuits.Furthermore, in one aspect of the invention, the programmable circuits66 ₀-66 ₃ incorporate antifuses (not shown in FIG. 7), and are thussimilar to the circuits 12 ₀-12 _(n) of FIGS. 1 and 2.

[0048] The bank 64 includes a program/test decoder circuit 68, whichselects the circuits 66 ₀-66 ₃ that are to be programmed during aprogramming mode or are to be tested during a conventional test mode. Atest circuit 70, which is coupled between a node 71 and ground,generates a test voltage or provides a test impedance during a digitaltest mode. The test circuit 70 may be similar to the test circuits 16 or47 of FIGS. 1 and 2. A normal-mode switch 78 couples the node 71 toground during normal operation of the bank 64. A program/test circuit 72provides a programming voltage during programming of the circuits 66₀-66 ₃, and provides a test voltage during the conventional test mode.In one aspect of the invention, the circuit 72 is a conductive pad towhich an external test circuit (not shown in FIG. 7) provides thedescribed programming and test voltages. A normal-mode/digital-test-modeswitch 74 couples a node 76 that is common to the circuits 66 ₀-66 ₃ tothe node 71 during normal operation and during the digital test mode. Aprogram-mode/conventional-test-mode switch 75 couples the common node 76to the program/test circuit 72 during programming or conventionaltesting of the bank 64. A logic circuit 79 receives the output signalsP₀-P₂ of the circuits 66 ₀-66 ₂, and logically combines them to generateresultant output signals L₀-L₇. A multiplexer 80 provides a selected oneof the signals L₀-L₇ and P₃ to an external terminal of the deviceincorporating the bank 64 during the digital test mode. A mode-controlcircuit 81 controls the operation of the switches 74, 75, and 78, andthe test circuit 70.

[0049] During the programming of the circuits 66 ₀-66 ₃, the decoder 68receives address signals at its address inputs and couples the selectedone of the circuits 66 ₀-66 ₃ to ground through a switching network 69.The switch 75 is active, and thus couples the common node 76 to theprogram/test circuit 72. Thus, in a manner similar to that describedabove in conjunction with FIG. 1, the circuit 72 generates a programvoltage and thus programs those of the circuits 66 ₀-66 ₃ that thedecoder 68 selects for programming.

[0050] During the conventional test mode, the circuit 72 generates atest voltage, and external test circuitry measures the current flowingthrough the circuit 66 under test to determine the resistance of theprogrammable element therein and whether or not it has a desired value.

[0051] During normal operation, the decoder 68 deactivates the switchingnetwork 69, the switches 74 and 78 are active, and the switch 75 isinactive. The bank 64 thus operates similarly to the banks 10 and 46,except that the signals P₀ -P₂ are not considered separately, but areconsidered as a predetermined logical combination. For example, thelogic circuit 79 may generate a selected one of the signals L₀-L₇ equalto logic 1, and the remainder of these signals equal to logic 0, whereeach one of the eight possible combinations of the three signals P₀-P₂selects a different one of the signals L₀-L₇ to equal logic 1. Thus,P₀-P₂ may be used together to select one of eight operational modes orcircuit configurations.

[0052] During the digital test mode of operation according to thepresent invention, the tester can test the bank 64 more quickly byreading the appropriate one of the signals L₀-L₇ instead of reading allof the signals P₀-P₂ individually. Specifically, the decoder 68 disablesall of the transistors in the switching network 69. The switch 74 isactive, and the switches 75 and 78 are inactive so that the test circuit70 can generate a test voltage or provide a test impedance at the commonnode 76. The digital testing then proceeds as discussed above inconjunction with FIG. 1. But instead of reading the signals P₀-P₂individually, the tester reads the one of the signals L₀-L₇ thatcorresponds to the correct programmed combination of P₀-P₂. For example,if the circuits 66 ₀-66 ₂ are programmed to generate the signals P₀-P₂equal to logic 1, logic 0, and logic 1, respectively, and this sequenceof values causes the logic circuit 79 to generate L₅ equal to logic 1,and L₀-L₄ and L₆-L₇ equal to logic 0, then the tester conventionallycontrols the multiplexer 80 to couple L₅ to the external read pin. If L₅equals logic 1, then the tester, with just this one reading, determinesthat all of the circuits 66 ₀-66 ₂ are properly programmed. Byeffectively testing more than one of the circuits 66 ₀-66 ₃simultaneously, the testing time can be significantly reduced ascompared with reading the signals P₀-P₃ sequentially. In another aspectof the invention, the multiplexer 80 may be omitted, and the tester candirectly probe the outputs of the logic gate L.

[0053]FIG. 8 is a schematic block diagram of a memory device 90, whichincorporates a programmable bank 92 according to the present invention.The programmable bank 92 may be similar to one of the banks 10, 46, 54or 64 of FIGS. 1, 2, 5 and 7, respectively. In one embodiment, thememory device 90 is a synchronous dynamic random access memory (SDRAM),although the inventive programmable bank 92 may be used in other typesof memories, and in integrated circuits other than memories, such asmicroprocessors.

[0054] In addition to the programmable bank 92, the memory device 90includes an address register 94, which receives an address from anaddress bus ADDRESS. A control logic circuit 96 receives CLK and COMMANDsignals, receives the programmed signals P from the programmable bank92, and communicates with and controls the other elements of the memorydevice 90.

[0055] A row-address multiplexer 98 receives the address signal from anaddress register 94, and provides the row address to row-addresslatch-and-decode circuits 100 a and 100 b. During read and write cycles,the row-address latch-and-decode circuits 100 a and 100 b activate theword lines of the addressed rows of memory cells in memory banks 102 aand 102 b, respectively. Read/write circuits 104 a and 104 b,respectively, read data from the addressed memory cells in the memorybanks 102 a and 102 b during a read cycle, and respectively write datato the addressed memory cells during a write cycle. A column-addresslatch-and-decode circuit 106 receives the address from the addressregister 94 and provides the column address of the selected memory cellsto the read/write circuits 104 a and 104 b. For clarity, the addressregister 94, the row-address multiplexer 98, the row-addresslatch-and-decode circuits 100 a and 100 b, and the column-addresslatch-and-decode circuit 106 can be collectively referred to as theaddress decoder.

[0056] A data input/output (I/O) circuit 108 includes a plurality ofinput buffers 110. During a write cycle, the buffers 110 receive andstore data from the DATA bus, and the read/write circuits 104 a and 104b, respectively, provide this stored data to the memory banks 102 a and102 b. The data I/O circuit 108 also includes a plurality of outputdrivers 112. During a read cycle, the read/write circuits 104 a and 104b respectively provide data from the memory banks 102 a and 102 b to thedrivers 112, which in turn provide this data to the DATA bus.

[0057] The memory device 90 may also include an optional charge pump114, which steps up the power-supply voltage V_(DD) to a voltageV_(DDP). In one aspect of the invention, the pump 114 generates V_(DDP)approximately 1 V to 1.5 V higher than V_(DD). The memory device 90 mayuse V_(DDP) to overdrive selected internal transistors in a conventionalmanner.

[0058] In operation, if the memory device 90 is a SDRAM, then all of theinput signals and output signals, as well as many of the internalsignals, are synchronized to the CLK signal. The control logic 96, inresponse to the programmed values P from the programmable bank 92,controls the operational modes of the memory device 90 in accordancewith these values. Additionally, the control logic 96 may also configurevarious circuits on the memory device 90 in response to the programmedvalues P. For example, redundant memory elements may be programmed to beresponsive to addresses of defective elements such as rows or columns ofmemory bits.

[0059] Alternatively, the programmable bank 92 may be coupled directlyto these configurable circuits, and thus supply the signals P directlythereto.

[0060]FIG. 9 is a schematic block diagram of a computer system 120,which incorporates the memory 90 of FIG. 8. The computer system 120includes computer circuitry 124 for performing computer functions, suchas executing software to perform desired calculations and tasks. Thecomputer circuitry 124 typically includes a processor 125 and the memorydevice 90, which is coupled to the processor 125. One or more inputdevices 126, such as a keypad or a mouse, are coupled to the computercircuitry 124 and allow an operator (not shown) to manually input datathereto. One or more output devices 128 are coupled to the computercircuitry 124 to provide the operator with the data generated by thecomputer circuitry 124. Examples of such output devices 128 include aprinter and a video display unit. One or more data-storage devices 130are coupled to the computer circuitry 124 to store data on or retrievedata from external storage media (not shown). Examples of the storagedevices 133 and the corresponding storage media include drives thataccept hard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). Typically, the computer circuitry 124 includesaddress, data, and command busses and a clock line that are respectivelycoupled to the ADDRESS, DATA, and COMMAND busses and the CLK line of thememory device 90.

[0061] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A programmable voltage divider having normal and test modes ofoperation, the divider comprising: first and second supply nodes; adivider node operable to provide a data value; a first divider elementcoupled between said first supply node and said divider node; acontrolled node; a second divider element coupled between said dividernode and said controlled node, said second divider element having aselectable resistivity; and a test circuit coupled between saidcontrolled node and said second supply node, said test circuit operableto generate a voltage at said controlled node during said normal mode ofoperation and to vary said voltage during said test mode of operation.2. The programmable voltage divider of claim 1 wherein: said testcircuit increases said voltage at said controlled node during said testmode; and said first and second divider elements are operable duringsaid test mode to generate said data value having a first logic levelwhen said second divider element has a resistivity that is less than orequal to a desired maximum value and to generate said data value havinga second logic level when said second divider element has a resistivitythat is greater than said desired maximum value.
 3. The programmablevoltage divider of claim 1 wherein: said test circuit decreases saidvoltage at said controlled node during said test mode; and said firstand second divider elements are operable during said test mode togenerate said data value having a first logic level when said seconddivider element has a resistivity that is greater than or equal to adesired minimum value and to generate said data value having a secondlogic level when said second divider element has a resistivity that isless than said desired minimum value.
 4. The programmable voltagedivider of claim 1 , further comprising a storage circuit that iscoupled to said divider node and that is operable to store said datavalue.
 5. The programmable voltage divider of claim 1 wherein said testcircuit comprises: a first switch coupled between said controlled nodeand said second supply node; a series combination of a second switch anda voltage source, said series combination coupled in parallel with saidfirst switch; and said test circuit operable during said test mode toopen said first switch and to close said second switch.
 6. Theprogrammable voltage divider of claim 1 wherein said test circuitcomprises: a first switch coupled between said controlled node and saidsecond supply node; a series combination of a second switch and animpedance element, said series combination coupled in parallel with saidfirst switch; and said test circuit operable during said test mode toopen said first switch and to close said second switch.
 7. Theprogrammable voltage divider of claim 1 wherein said test circuitcomprises: a first switch coupled between said controlled node and saidsecond supply node; a diode coupled in series with a second switch, theseries combination of said second switch and said diode coupled parallelwith said first switch; and said test circuit operable during said testmode to open said first switch.
 8. A programmable voltage divider havingnormal and test modes of operation, the divider comprising: first andsecond supply nodes; a divider node operable to provide a data value; afirst divider element coupled between said first supply node and saiddivider node; a controlled node; a second divider element coupledbetween said divider node and said controlled node and having aprogrammable conductivity; and a variable impedance coupled between saidcontrolled node and said second supply node, said variable impedancehaving a larger value during said test mode than during said normalmode.
 9. The programmable voltage divider of claim 8 wherein saidvariable impedance comprises: a first switch coupled between saidcontrolled node and said second supply node; a series combination of asecond switch and an impedance element, said series combination coupledin parallel with said first switch; and said variable impedance operableduring said test mode to open said first switch and to close said secondswitch.
 10. The programmable voltage divider of claim 8 wherein saidfirst and second divider elements are operable during said test mode togenerate said data value having a first logic level when said seconddivider element has a conductivity that is greater than or equal to aselected minimum value and to generate said data value having a secondlogic level when said second divider element has a conductivity that isless than said selected minimum value.
 11. The programmable voltagedivider of claim 8 , further comprising programming circuitry that iscoupled across said second divider element and that is operable toprogram said second divider element to have a first conductivity. 12.The programmable voltage divider of claim 8 wherein said first dividerelement is a transistor.
 13. A circuit for providing a programmablereference value, the circuit comprising: first and second supplyterminals; a reference node that provides said reference value; a testnode; a first impedance element having a first terminal coupled to saidfirst supply terminal and having a second terminal coupled to saidreference node; a selectively conductive element having a first terminalcoupled to said reference node and having a second terminal coupled tosaid test node; a first switch coupled between said test node and saidsecond supply terminal; a second switch having a first terminal coupledto said test node and having a second terminal; and a second impedanceelement coupled between said second terminal of said second switch andsaid second supply terminal.
 14. The circuit of claim 13 wherein: saidfirst impedance element comprises a transistor; and said secondimpedance element comprises a resistor.
 15. The circuit of claim 13wherein said selectively conductive element comprises an antifuse. 16.The circuit of claim 13 , further comprising: said first and secondswitches each having a control terminal; and a control circuit that iscoupled to said control terminals of said first and second switches. 17.The circuit of claim 13 , further comprising an isolation device that isserially coupled between said reference node and said first terminal ofsaid selectively conductive element.
 18. The circuit of claim 13 ,further comprising: a decoder circuit coupled to said first terminal ofsaid selectively conductive element; and a program-voltage generatorcoupled to said second terminal of said selectively conductive element.19. A circuit for providing a selectable reference value, the circuitcomprising: first and second supply terminals; a reference node thatprovides said reference value; a test node; an impedance element havinga first terminal coupled to said first supply terminal and having asecond terminal coupled to said reference node; an element having aprogrammable conductivity, said programmable element including a firstterminal coupled to said reference node and having a second terminalcoupled to said test node; a first switch coupled between said test nodeand said second supply terminal; and a voltage source coupled betweensaid test node and said second supply terminal.
 20. The circuit of claim19 , further comprising: a second switch having a first terminal coupledto said test node and having a second terminal; and said voltage sourcecoupled between said second terminal of said second switch and saidsecond supply terminal.
 21. The circuit of claim 19 wherein saidprogrammable element comprises a laser fuse.
 22. The circuit of claim 19wherein said programmable element comprises an electrical fuse.
 23. Thecircuit of claim 20 wherein said voltage source has a positive terminalcoupled to said second terminal of said second switch and has a negativeterminal coupled to said second supply terminal.
 24. The circuit ofclaim 20 wherein said voltage source has a negative terminal coupled tosaid second terminal of said second switch and has a positive terminalcoupled to said second supply terminal.
 25. The circuit of claim 19 ,further comprising a latch having an input terminal coupled to saidreference node, said latch storing said reference value and providingsaid stored reference value on an output terminal.
 26. The circuit ofclaim 19 , further comprising: an initialization switch coupled betweensaid first supply terminal and said first terminal of said impedanceelement; a latch switch coupled in parallel with said initializationswitch, said latch switch having a control terminal; and an invertercoupled between said reference node and said control terminal of saidlatch switch.
 27. The circuit of claim 19 wherein said voltage sourcecomprises a transistor that is connected in a diode configuration. 28.The circuit of claim 19 , further comprising an isolation transistorserially coupled between said reference node and said first terminal ofsaid programmable element.
 29. A device for providing a plurality ofprogrammable values, the device comprising: first and second supplyterminals; a common node; a plurality of programmable circuits, eachcomprising, a reference node that provides one of said programmablevalues, an impedance element having a first terminal coupled to saidfirst supply terminal and having a second terminal coupled to saidreference node, and a programmable element having a first terminalcoupled to said reference node and having a second terminal coupled tosaid common node; a normal-mode switch coupled between said common nodeand said second supply terminal; a test circuit coupled between saidcommon node and said second supply terminal; and a logic circuit havinga plurality of input terminals coupled to more than one of saidreference nodes and having an output terminal, said logic circuitoperable to logically combine said reference values on said inputterminals into a combined reference signal on said output terminal. 30.The device of claim 29 wherein said test circuit comprises: a test-modeswitch having a first terminal coupled to said common node and having asecond terminal; and a voltage generator coupled between said secondterminal of said test-mode switch and said second supply terminal. 31.The device of claim 29 , further comprising: a program decoder coupledto said reference nodes of said programmable circuits and to said secondsupply terminal, said decoder operable to couple the programmableelement of a selected one of said programmable circuits in a programconfiguration during a program mode; and a programmer coupled to saidcommon node and operable to program said programmable element of saidselected programmable circuit during said program mode.
 32. The deviceof claim 29 , further comprising: a normal-mode/test-mode switch coupledbetween said common node and both said normal-mode switch and said testcircuit; a programmer; a program-mode switch coupled between saidprogrammer and said common node; and a program decoder having at leastone address input terminal, said decoder including decoder logic coupledto said address input terminal and including a plurality of switches,each switch coupled between one of said reference nodes and said secondsupply terminal and having a control terminal coupled to said decoderlogic.
 33. A memory device, comprising: first and second supply nodes;address, data, and command busses; a bank of memory cells; an addressdecoder coupled to said address bus and said memory bank; a controlcircuit coupled to said command bus and to said address decoder; aread/write circuit coupled to said address decoder, control circuit, andmemory bank; a data input/output circuit coupled to said data bus,read/write circuit, and control circuit; and a programmable voltagedivider having normal and test modes of operation, the dividercomprising, a divider node operable to provide a reference value, afirst divider element coupled between said first supply node and saiddivider node, a controlled node, a second divider element coupledbetween said divider node and said controlled node, said second dividerelement having a selectable resistivity, and a test circuit coupledbetween said controlled node and said second supply node, said testcircuit operable to generate a voltage at said controlled node duringsaid normal mode of operation and to vary said voltage during said testmode of operation.
 34. The memory device of claim 33 wherein: said testcircuit increases said voltage at said controlled node during said testmode; and said first and second divider elements are operable duringsaid test mode to generate said data value having a first logic levelwhen said second divider element has a resistivity that is less than orequal to a desired maximum value and to generate said data value havinga second logic level when said second divider element has a resistivitythat is greater than said desired maximum value.
 35. The programmablevoltage divider of claim 33 wherein: said test circuit decreases saidvoltage at said controlled node during said test mode; and said firstand second divider elements are operable during said test mode togenerate said data value having a first logic level when said seconddivider element has a resistivity that is greater than or equal to adesired minimum value and to generate said data value having a secondlogic level when said second divider element has a resistivity that isless than said desired minimum value.
 36. The memory device of claim 33wherein said test circuit comprises: a first switch coupled between saidcontrolled node and said second supply node; a series combination of asecond switch and a fixed voltage source, said series combinationcoupled in parallel with said first switch; and said test circuitoperable during said test mode to open said first switch and to closesaid second switch.
 37. The memory device of claim 33 wherein said testcircuit comprises: a first switch coupled between said controlled nodeand said second supply node; a series combination of a second switch andan impedance element, said series combination coupled in parallel withsaid first switch; and said test circuit operable during said test modeto open said first switch and to close said second switch.
 38. Thememory device of claim 33 wherein said second divider element comprisesan antifuse.
 39. The memory device of claim 33 wherein said seconddivider element comprises a laser-cuttable fuse.
 40. The memory deviceof claim 33 wherein said second divider element comprises anelectrically blowable fuse.
 41. The memory device of claim 33 whereinsaid second divider element comprises an electrically erasable andprogrammable cell.
 42. A computer system, comprising: a data inputdevice; a data output device; and computing circuitry coupled to saiddata input and output devices, said computing circuitry including amemory device that includes, first and second supply nodes, address,data, and command busses, a bank of memory cells, an address decodercoupled to said address bus and said memory bank, a control circuitcoupled to said command bus and to said address decoder, a read/writecircuit coupled to said address decoder, control circuit, and memorybank, a data input/output circuit coupled to said data bus, read/writecircuit, and control circuit, and a programmable voltage divider havingnormal and test modes of operation, the divider comprising, a dividernode operable to provide a programmed value, a first divider elementcoupled between said first supply node and said divider node, a testnode, a second divider element coupled between said divider node andsaid test node, said second divider element having a selectableresistivity, and a test circuit coupled between said test node and saidsecond supply node, said test circuit operable to generate a voltage atsaid test node during said normal mode of operation and to vary saidvoltage during said test mode of operation.
 43. The computer system ofclaim 42 wherein: said test circuit increases said voltage at said testnode during said test mode; and said first and second divider elementsare operable during said test mode to generate said programmed valuehaving a first logic level when said second divider element has aresistivity that is less than or equal to a desired maximum value and togenerate said programmed value having a second logic level when saidsecond divider element has a resistivity that is greater than saiddesired maximum value.
 44. The computer system of claim 42 wherein: saidtest circuit decreases said voltage at said test node during said testmode; and said first and second divider elements are operable duringsaid test mode to generate said programmed value having a first logiclevel when said second divider element has a resistivity that is greaterthan or equal to a desired minimum value and to generate said programmedvalue having a second logic level when said second divider element has aresistivity that is less than said desired minimum value.
 45. Thecomputer system of claim 42 wherein said test circuit comprises: a firstswitch coupled between said test node and said second supply node; aseries combination of a second switch and a fixed voltage source, saidseries combination coupled in parallel with said first switch; and saidtest circuit operable during said test mode to open said first switchand to close said second switch.
 46. The computer system of claim 42wherein said test circuit comprises: a first switch coupled between saidtest node and said second supply node; a series combination of a secondswitch and an impedance element, said series combination coupled inparallel with said first switch; and said test circuit operable duringsaid test mode to open said first switch and to close said secondswitch.
 47. A method for testing the conductivity of a programmedconduction element, the method comprising: coupling an impedance betweena constant voltage and a first terminal of said programmed element;generating at a second terminal of said programmed element a testvoltage; and comparing the voltage at said first terminal of saidprogrammed element to a predetermined voltage to determine if saidconductivity of said programmed element is within a desired range. 48.The method of claim 47 wherein said generating comprises coupling avoltage generator between said second terminal of said programmedelement and said reference voltage.
 49. The method of claim 47 whereinsaid generating comprises coupling a load between said second terminalof said programmed element and a reference voltage.
 50. A method,comprising: setting a fuse element having a variable impedance to alow-impedance state; pulling up a first node of said fuse element to afirst reference voltage via an impedance element; coupling a testvoltage to a second node of said fuse element; comparing a resultantvoltage at said first node with a threshold voltage; and if saidresultant voltage is greater than said threshold voltage, failing saidfuse element as having an impedance that is too high.
 51. The method ofclaim 50 wherein said test voltage is greater than a voltage that iscoupled to said second node during normal operation of said fuseelement.
 52. The method of claim 50 wherein said coupling comprisescoupling a test impedance between said second node of said fuse elementand a reference node.
 53. The method of claim 50 wherein said couplingcomprises coupling a positive voltage to said second node.
 54. Themethod of claim 50 wherein said fuse element is an antifuse.
 55. Amethod, comprising: setting a fuse element having a variable impedanceto a high-impedance state; pulling up a first node of said fuse elementto a first reference voltage via an impedance element; coupling a testvoltage to a second node of said fuse element; comparing a resultantvoltage at said first node with a threshold voltage; and if saidresultant voltage is less than said threshold voltage, failing said fuseelement as having an impedance that is too low.
 56. The method of claim55 wherein said test voltage is less than a voltage that is coupled tosaid second node during normal operation of said fuse element.
 57. Themethod of claim 55 wherein said coupling comprises coupling a negativevoltage to said second node.
 58. The method of claim 55 wherein saidfuse element is a laser fuse.
 59. The method of claim 55 wherein saidfuse element is an electrical fuse.
 60. A method for testing theconductivities of programmed conduction elements, the method comprising:for each of said programmed conduction elements, coupling an impedancebetween a constant voltage and a first terminal of said each programmedelement; generating at second terminals of said programmed elements atest voltage; logically combining the logic levels at said firstterminals of said programmed elements to generate a resulting logiclevel; and comparing said resulting logic level to a predetermined logiclevel to determine if said conductivities of said programmed elementsare within a desired range.
 61. The method of claim 60 wherein saidgenerating comprises coupling a voltage generator between said secondterminals of said programmed elements and a reference voltage.
 62. Themethod of claim 60 wherein said generating comprises coupling a loadbetween said second terminals of said programmed elements and areference voltage.
 63. A method of testing the programmed impedance of aprogrammable circuit element comprising: coupling a first terminal ofthe programmable circuit element to a first voltage; coupling a secondterminal of the programmable circuit element to a second voltage througha circuit element, the circuit element having a test mode and a normaloperating mode, the circuit element altering the voltage on the secondterminal of the programmable circuit element between the test and normaloperating modes; and examining the voltage on the second terminal of theprogrammable circuit element during the test mode.
 64. The method ofclaim 63 wherein the circuit element comprises a variable voltagesource.
 65. The method of claim 63 wherein the circuit element comprisesa variable impedance.